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2013년

Publications: 2013년
 
논문
 
- Y.S. Ryu, "Performance Evaluation of Page Migration Scheme for NVRAM-based Wireless Sensor Nodes," International Journal of Distributed Sensor Networks, Hindawi, Nov. 2013.
 
- S.H. Yang, Y.S Ryu, "A Buffer  Management for STT-MRAM based Hybrid Main Memory in Sensor Nodes," International Conference on Computer, Networks and Communication Engineering, Beijing, China, pp. 286-289, May, 2013.
 
M.H. Shin, R. A. Memon, Y.S. Ryu, J.M. Rhee, D.H. Lee, "A Fault-tolerant Network Scheme for Large-scale Mission-critical Systems,"  Information Journal, Vol. 16, No. 3(B), pp. 3285-3290, Mar. 2013.

J.H. Ahn, Y.S. Ryu, D.K. Baik, "An Acknowledged System of Systems Architecture Description Method," Information Journal, Vol. 16, No. 3(B), pp. 3177-3182, Mar. 2013.
 
- S.H. Yang, Y.S. Ryu, "A Block-level Buffer Cache Management Scheme for NAND Flash Memory Storages," Information Journal, Vol. 16, No. 2(B), pp. 1531-1536, Feb. 2013.
 
- S.H. Yang, Y.S. Ryu, "A Buffer Cache Scheme Considering both DRAM/PRAM Hybrid Main Memory and Flash Memory Storages," International Conference on Pervasive and Embedded Computing and Communication Systems, Barcelona, Spain, Feb. 2013.
 
- S. H. Yang, Y.S. Ryu, "DRAM/MRAM 하이브리드 메인 메모리와 플래시 메모리 저장장치를 고려한 버퍼 캐시 기법," Korea Information Processing SOciety Spring Conference, pp. 93-96, May, 2013.
 
저서
 
- Y.S. Ryu, et.al., "Computer Security - Principles ans Practice," August. 2013.
 
특허
 
"Apparatus and Method for Managing Buffer Considering Memory Erase Block," Korea Patent # 10-1288276, July 15, 2013.

"A Buffer Cache Method for considering both Hybrid Main Memory and Flash Memory Storages," Korea Patent Application # 10-2013-0064098, June 4, 2013.